Flucta

A hardware lab for probabilistic computing

We are buildinga new class of computer

Flucta invents probabilistic algorithms and designs the hardware around them. Our algorithms change what a machine needs to compute, which data it needs to read, and how often its processors need to communicate. They run on NVIDIA GPUs today, and our own FPGA accelerator runs models end to end.

250:1

Energy to read a byte vs. compute on it

0

Retraining or fine-tuning needed to deploy

Near-dense

accuracy in our benchmarks, vs. the dense baseline

2027

SPU tapeout, 7 nm custom silicon

Why a new class of computer

Reading a byte costs 250× more than computing on it.

On a modern accelerator, reading one byte from HBM costs roughly 25 picojoules; computing on it costs about 0.1. We found that models tolerate substantial sparsity: in attention, in experts, in long contexts, a small fraction of the bytes carries the answer. Our algorithms already use that tolerance on GPUs, and they run into the machine itself: a GPU is architected for dense execution and cannot exploit sparsity in full. That is why Flucta is building its own hardware, as the only hardware company that designs the algorithm and the processor as one.

Memory

HBM · hundreds of GB

KV cache, weights

bytes the model needs

Memory interface

Bottleneck25 pJ / byte

Compute die

0.1 pJ / byte

Waits on memory most of every token

Bytes the model needs

a small fraction

Bytes dense hardware reads

all, every token

250×

move ≫ compute

Widening the bus and stacking more memory does not remove the overhead: dense hardware still reads bytes the model never needed.

Flucta is redesigning compute, data movement and connectivity around that tolerance: the machine performs selected work, reads selected data, and communicates less often.

The same answerfrom a fraction of the reads.

Paris
Reads / tokenthe whole context

Legacy · Dense Read

Reads everything, every token

VS

Paris
Reads / tokena small fraction

Flucta · Sampled Read

Reads only what carries signal

From algorithms to FPGAs to purpose-built silicon.

The speedups run as software on today's GPUs, with no retraining. The same kernels are moving onto FPGA prototypes now, and measurements from that hardware drive the Stochastic Processing Unit: purpose-built ASICs first, then 3D-stacked memory-on-logic. Every stage runs the same probabilistic abstraction on hardware with less overhead than the stage before.

Where we’re going

Today

End-to-End Probabilistic Algorithms

Running on GPUs today · FPGA validated · ICML 2026

Early 2027

SPU tapeout

7 nm · custom memory hierarchy

2028

3D-stacked SPU

Near-memory compute · datacenter

Physicists and chip architects, building from first principles.

Flucta's founders started the field of probabilistic computing with p-bits, and many of the field's Nature-level firsts are theirs: the first demonstration of 1,000,000 p-bits, the first carbon nanotube computer, and firsts in 3D chips and in hardware/software co-design.

KÇ

Kerem Y. Çamsarı

Co-founder & CEO · Professor, UCSB (ex-Purdue)

  • Co-inventor of the p-bit (Nature 2019)
  • Landmark Nature paper with 2025 Nobel Laureate John Martinis
  • $25M+ federal research as PI
TS

Tathagata Srimani

Co-founder & Research Scientist · Assistant Professor, CMU (ex-MIT/Stanford)

  • First carbon nanotube computer (Nature 2019)
  • Co-PI, $40M DoD AI hardware program, 40+ chip tapeouts
  • Led lab-to-fab transition of carbon nanotubes

Founding team

* Consulting
KP
Silicon

Kartik Prabhu

Ph.D., Stanford

SC
Algorithm / Kernel

Shuvro Chowdhury

Ph.D., Purdue

CD
Algorithm / Kernel

Corentin Delacour*

Ph.D., Univ. of Montpellier

KS
Algorithm / Kernel

Kemal Selçuk

Ph.D., UC Santa Barbara

NS
Algorithm / Kernel

Nihal Sanjay Singh

Ph.D., UC Santa Barbara

KB
Silicon

Kai Bartolone

M.S., Stanford

KC
Silicon

Kevin Callahan-Coray

Ph.D. Candidate, UC Santa Barbara

EC
Silicon

Eric Cheng

M.S. Candidate, Stanford

ZH
Inference Serving

Zengxiao He

M.S., Stanford

OY
Research Consultant

Osman Yağan

Professor of ECE, Carnegie Mellon

NS
Research Consultant

Nikhil Shukla

Associate Professor of ECE, UVA

Advisors

SM

Subhasish Mitra

Stanford

Professor of EE & Computer Science · Robust Systems Group

SL

Suk Hwan Lim

ex-Google

Former Corporate EVP, Samsung Semiconductor

Funded by investors
who back foundational technology.

South Park Commons
Moxxie Ventures
Pear VC
Humba Ventures
Defined

Frequently Asked Questions

Flucta builds probabilistic computing across the stack. Our algorithms and runtime speed up inference end to end on today's GPUs, with accuracy close to the dense baseline in our benchmarks, and the same principles carry into FPGA prototypes and purpose-built silicon.

Chip companies optimize for algorithms as they find them, and algorithm companies optimize within the silicon they are given. Flucta designs the algorithm, the runtime and the processor as one system. The orders-of-magnitude gains live between those layers, and a company that owns only one layer cannot reach them.

Not initially. Though our principles will naturally lead us there in terms of custom ASICs, 3D-CMOS, and near-memory computation, our initial focus operates at the system and architectural level. Instead of waiting on novel physical devices, we re-architect memory hierarchies, routing logic, and execution pipelines on standard silicon processes to natively support sampling and probabilistic operations today.

Enormous efficiency is lost between the design abstractions of the modern stack. Algorithms are written as if moving memory were free, runtimes assume dense and deterministic execution, and silicon is built for worst-case precision. Each boundary hides what the layer below actually needs, and the waste compounds. Flucta removes these boundaries with a top-down design philosophy, carrying one probabilistic abstraction from the algorithm through the runtime into the silicon, so the gains at each layer multiply.

Email founders@flucta.ai to request the technical brief. We are hiring first-principles thinkers across physics, computer science, computer engineering, kernel development, and inference optimization.